A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
Proceedings of the 41st annual Design Automation Conference
Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits
IEEE Design & Test
Software-based self-test methodology for crosstalk faults in processors
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
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With the semiconductor industry evolving into the deepsub-micron (DSM) era, crosstalk noise becomes a criticalissue that needs to be handled efficiently and accurately.Modern designs like System-on-Chips have millions ofnoise-prone wires that need to be analyzed. Analysis usingcircuit-level simulation is not feasible. Efficient static noiseanalysis, which statically estimate noise based on linearcircuit model, is widely used. However, traditionallydrivers' holding resistances are pre-characterized withoutconsidering the crosstalk noise. The driver's holdingresistance changes dramatically with the crosstalk noiseinduced voltage changing on the victim wire. For accuratenoise estimation, the driver's substantial nonlinear variationcannot be ignored. In this paper, we propose a novelmethod, which uses layout extracted parameters ofcoupling interconnect and pre-characterized parameters ofdriver to calculate an effective holding resistance. Thenoise-aware effective holding resistance dramaticallyimproves the accuracy for noise magnitude and energyestimation. The proposed method is simple and efficient. Itenables fast on-the-fly calculation of the effective holdingresistance. Experiments show significant improvement inaccuracy with almost negligible computation overhead.