Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
A low-power design method using multiple supply voltages
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Low-swing clock domino logic incorporating dual supply and dual threshold voltages
Proceedings of the 39th annual Design Automation Conference
CMOS Logic Circuit Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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Domino logic is used extensively in high speed microprocessor datapath design. Although domino gates have small propagation delay, they consume relatively more power. We propose a scheme to reduce the power consumption of combinational domino logic blocks while maintaining the performance. We replace the PMOS precharge transistor with an NMOS transistor to reduce the overall power consumption of the gate at the expense of higher delay. We use a heuristic algorithm to replace the fast, high power gates on the off-critical paths with slower, low power gates while maintaining the circuit performance. Our technique reduces dynamic energy of ISCAS'85 circuits by 16.25%.