A low-power design method using multiple supply voltages
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Mixed-swing quadrail for low power dual-rail domino logic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
On gate level power optimization using dual-supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Converter-free multiple-voltage scaling techniques for low-power CMOS digital design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reduced dynamic swing domino logic
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Elements of low power design for integrated systems
Proceedings of the 2003 international symposium on Low power electronics and design
Low-power dual Vth pseudo dual Vdd domino circuits
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Low-power domino circuits using NMOS pull-up on off-critical paths
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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High-speed domino logic is now prevailing in performance critical block of a chip. Low Voltage Swing Clock (LVSC) domino logic family is developed for substantial dynamic power saving. To boost up the transition speed in proposed circuitry, a well-established dual threshold voltage technique is exploited. Dual supply voltage technique in the LVSC domino logic is geared to reduce power consumption in clock tree and logic gates effectively. Delay Constrained Power Optimization (DCPO) algorithm allocates low supply voltage to logic gates such that dynamic power consumed by logic gates is minimized. Delay time variations due to gate-to-source voltage change and and input signal arrival time difference are considered for accurate timing analysis in DCPO.