An introduction to signal detection and estimation (2nd ed.)
An introduction to signal detection and estimation (2nd ed.)
Randomized algorithms
Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
A low-power design method using multiple supply voltages
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Delay Testing of Digital Circuits by Output Waveform Analysis
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Ultra-Low Energy Computing with Noise: Energy-Performance-Probability Trade-offs
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Error-resilient motion estimation architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Maintaining the benefits of CMOS scaling when scaling bogs down
IBM Journal of Research and Development
Inexact computing using probabilistic circuits: Ultra low-power digital processing
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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We elaborated a new ultra low-power nanometer circuit design methodology by introducing statistical fluctuations in advanced technology nodes as noise sources causing computational errors. The modeling is performed on sub-50 nm technology node to create a statistical performance metric. The relationship between the probability of error and the circuit noise for a variety of different configurations and of circuit topologies is explored. Input-coupled noise has the dominant effect in terms of error and is analyzed through AC and high-frequency properties of the inverter transfer characteristics. Gate-level implementation of the probabilistic CMOS logic is validated with circuit simulations using a commercial 45-nm SOI CMOS process technology. Using a 32-bit adder where voltages can be scaled from MSB to LSB as an example, simulation results show the power of the technique. A calculation error of 10−6, a number quite appropriate for many computational tasks, occurs with a total power reduction of more than 40 %.