Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The interdependence between delay-optimization of synthesized networks and testing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
A fully implicit algorithm for exact state minimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Two-Pattern Test Capabilities of Autonomous TPG Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Error Control Coding, Second Edition
Error Control Coding, Second Edition
LFSR-Based Deterministic TPG for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An optimized BIST test pattern generator for delay testing
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
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A cost-effective built-in self testing (BIST) method for the detection of delay faults is presented. A multiple-input signature register (MISR) with a constant parallel input vector is used as a test pattern generator. To reduce the test length of the MISR, a two-step approach is proposed. First, deterministic delay test generation is employed to determine a set of two-pattern tests which detect all testable path delay faults. Second, a minimal number of constant MISR input vectors is calculated such that the state sequences generated by the MISR include the pre-determined test set. The second step is formulated as a set covering problem. As the number of MISR input vectors may be exponential in the number of stages of the MISR, their calculation and the set covering are performed implicitly with BDDs. Experimental results reveal that in almost all considered cases a maximum robust path delay fault coverage is obtained with less than 100 MISR input vectors.