ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults
ITC '00 Proceedings of the 2000 IEEE International Test Conference
SPIRIT: A Highly Robust Combinational Test Generation Algorithm
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Conflict driven techniques for improving deterministic test pattern generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Estimation of delay test quality and its application to test generation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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In this work, a new and effective procedure, called REDI, to efficiently identify redundant single stuck-at faults in combinational logic circuits is proposed. The method is fault oriented and uses sensitizability of partial paths to determine redundant faults. It uses only implications and hence may not determine all the redundant faults of a circuit. However, experimental results presented on benchmark circuits show that the procedure identifies nearly all the redundant faults in most of the benchmark circuits. The key features of REDI that make it efficient are: partial path sensitization, blockage learning, dynamic branch ordering and fault grouping. Experimental results on benchmark circuits demonstrate the efficiency of the proposed procedure in identifying redundant faults in combinational logic circuits.