Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Exact calculation of synchronization sequences based on binary decision diagrams
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Algorithms for approximate FSM traversal
DAC '93 Proceedings of the 30th international Design Automation Conference
Symbolic exploration of large circuits with enhanced forward/backward traversals
EURO-DAC '94 Proceedings of the conference on European design automation
A Test-Pattern-Generation Algorithm for Sequential Circuits
IEEE Design & Test
Efficient State Space Pruning in Symbolic Backward Traversal
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Verification of Synchronous Sequential Machines Based on Symbolic Execution
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Fast Sequential ATPG Based on Implicit State Enumeration
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Sequential Test Generation Based on Real-Value Logic
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
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Until now, symbolic FSM state space exploration techniques were limited to small circuits. This paper presents a combination of approximate forward and exact backward traversal that handles larger circuits. For the first time, we have been able to generate test patterns for or to tag as undetectable the faults of some ISCAS'89 and MCNC benchmarks never considered before.