Distributed Implementation of an ATPG System Using Dynamic Fault Allocation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Workstation Based Parallel Test Generation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Parallel test generation with low communication overhead
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
An adaptive distributed algorithm for sequential circuit test generation
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Coarse-Grain Parallelization of Test Vectors Generation on Multiprocessor Systems
IWCC '01 Proceedings of the NATO Advanced Research Workshop on Advanced Environments, Tools, and Applications for Cluster Computing-Revised Papers
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We present a distributed algorithm for automatic test generation for sequential circuits. Our system uses a network of workstations by partitioning the fault list. Multiple test generation processes are run on separate processors. Unlike a prior implementation, the communication of detected faults among processors is asynchronous, with all computers processing and broadcasting detected faults without synchronization. We thus accomplish a reduction in duplicated computation and a general improvement in the speedup as compared to the synchronized parallelization. Experimental results demonstrate superlinear speedups for some of the benchmark circuits. A mathematical model is presented to explain the speedups.