A parallel branch and bound algorithm for test generation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An adaptive distributed algorithm for sequential circuit test generation
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
An asynchronous algorithm for sequential circuit test generation on a network of workstations
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
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In this paper we present a method of parallelizing test generation for combinational logic using boolean satisfiability. We propose a dynamic search-space allocation strategy to split work between the available processors. This strategy is easy to implement with a greedy heuristic and is economical in its demand for inter-processor communication. We derive an analytical model to predict the performance of the parallel versus sequential implementations. The effectiveness of our method and analysis is demonstrated by an implementation on a Sequent (shared memory) multiprocessor. The experimental data shows significant performance improvement in parallel implementation, validates our analytical model, and allows predictions of performance for a range of time-out limits and degrees of parallelism.