An asynchronous algorithm for sequential circuit test generation on a network of workstations
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
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The paper describes parallel implementation of automatic test vectors generation on multiprocessor systems using Boolean Difference Algorithm. The analysis of the algorithm points out that coarse-grain parallelization involves two types of data-dependencies that require different techniques for removing them: circuit model replication and mutual exclusion mechanisms. Toward balancing load of the work among processors, static and dynamic partitioning of computational task is studied. For each parallelization strategy, the theoretical speedup is estimated in order to select the most efficient implementation. The estimated and measured results show that the speed of automatic test generation can be significantly increased with parallel approach and this is an important achievement in the present technological context, with wide availability of multiprocessors stations.