A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
An Efficient Algorithm for Sequential Circuit Test Generation
IEEE Transactions on Computers
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Sequential Circuit Output Probabilities From Regular Expressions
IEEE Transactions on Computers
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
Combinational ATPG theorems for identifying untestable faults in sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We propose a new method to significantly accelerate sequential test generation algorithms. The main idea is to accurately compute signal constraints for large sequential circuits and use these constraints effectively during deterministic sequential test generation. Our signal constraint computation technique is based on three key Ideas: (1) unlike prior techniques (which compute line probabilities assuming only a 0 or 1 logic value for any signal), line probabilities are computed by allowing signals to assume values other than 0 or 1, (2) line justification techniques are employed to update line probabilities, and (3) symbolic simulation is iteratively used in conjunction with line probability computation and line justification to refine the set of values that a signal can assume. Experimental results on several large production and benchmark sequential circuits show that our technique results in a significant reduction (more than 50%) in the test generation time. This reduction is achieved without compromising the fault coverage that can be obtained by the base system. By incorporating our technique into the base system, we obtained higher fault coverage using fewer CPU seconds for a majority of example sequential circuits.