On probabilistic switch-level simulation for asynchronous circuits

Authors:
Suresh Rajgopal;Akhilesh Tyagi
Affiliations:
University of North Carolina, Chapel Hill, NC;University of North Carolina, Chapel Hill, NC
Venue:
EURO-DAC '91 Proceedings of the conference on European design automation
Year:
1991

Citing 2
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Abstract

The delay information useful in asynchronous circuits is not the same as in synchronous circuits. Rather than using the worst case delay, usually computed by a critical path analysis, the average case delay over a set of input assignments is a more relevant parameter for an asynchronous system. We present a novel, probability-propagation based algorithm to compute the average case switch-level delays. We discuss an implementation of this algorithm which is built on top of RNL, an event-driven switch-level simulator. This implementation takes the same order of time that RNL takes to simulate for one input assignment for determining the average case delays.