Bounding Signal Probabilities in Combinational Circuits
IEEE Transactions on Computers
Improved Techniques for Estimating Signal Probabilities
IEEE Transactions on Computers
STAFAN: An alternative to fault simulation
DAC '84 Proceedings of the 21st Design Automation Conference
Evaluating FTRE's for Dependability Measures in Fault Tolerant Systems
IEEE Transactions on Computers - Special issue on fault-tolerant computing
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An algorithm for bounding the random pattern testability of individual faults in a circuit is proposed. Auxiliary gates for bounding the testability are constructed, converting the problem into one of determining the signal probability at the output of the auxiliary gate. The results presented are in terms of lower bounds of the testabilities of faults. The bounds generated by the algorithm can be used by designers to identify pseudorandom pattern resistant faults, to enable them to modify the circuit structure to make the faults easy to detect, and, hence, to increase the fault coverage.