A New Method for Testing Re-Programmable PLAs

Authors:
Charles E. Stroud;James R. Bailey;Johan R. Emmert
Affiliations:
Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, Charlotte, NC 28223, USA. cestroud@uncc.com;Department of Electrical Engineering, University of Kentucky, Lexington, KY 40506, USA;Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, Charlotte, NC 28223, USA
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2000

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Abstract

We present a method for obtaining a minimal set of test configurations and their associated set of test patterns that completely tests re-programmable Programmable Logic Arrays (PLAs) including EEPROM, UV-EPROM, and SRAM based re-programmable PLAs typically found in Complex Programmable Logic Devices (CPLDs). The resultant set of test configurations and vectors detect all single and multiple stuck-at faults (including line and transistor faults) as well as all bridging faults in the PLA. Previously proposed test methods proposed for EEPROM based PLAs (IEEE Trans. on CAD, Vol. 13, No. 7, pp.935–939, 1994;Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1998, pp. 146–154) require additional test hardware as well as a large number of test configurations and vectors for complete testing. Our approach requires no modification to the PLA and only two or four test configurations, depending on the ratio of PLA product terms to inputs.