Testing programmable logic arrays by sum of syndromes
IEEE Transactions on Computers
Self-checking alternating logic: Sequential circuit design
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
DAC '78 Proceedings of the 15th Design Automation Conference
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
Detection of Faults in Programmable Logic Arrays
IEEE Transactions on Computers
Fault Detection Capabilities of Alternating Logic
IEEE Transactions on Computers
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This paper presents a new technique to convert a PLA into a testable PLA. Only one extra input, one extra product line, and one extra output are added for the augmented PLA. The augmented PLA can operate in three modes: the normal operating mode, the self-checking mode, and the universal syndrome testing mode. In the normal operating mode, the augmented PLA acts as the naked PLA. In the self-checking mode, the alternating code is used and has the advantage of short error-detection delay, wide fault set, and the ability to fully exercise the checker. In the universal syndrome testing mode, the universal weighted sum of syndromes is applied for off-line diagnosis. The universal weighted sum of syndromes is only dependent on the number of inputs and outputs of the augmented PLA, and does not deal with the realized function of the PLA. The universal weighted sum of syndromes is very suitable for the built-in self-testing technique. Since PLAs are usually components of VLSI chips, the built-in self-testing feature is very important for complex PLAs.