Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Innovative Structures for CMOS Combinational Gates Synthesis
IEEE Transactions on Computers
Logic synthesis through local transformations
IBM Journal of Research and Development
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A new methodology for multiple-output functions synthesis at transistor level is presented. The final network produces the defined output values by creating a set of connections among source, ground and output nodes not necessarily implementing specific subcircuits constituting each single function. Area minimization and timing constraints are figures of merit for the quality of the proposed solution. Application results for a set of randomly generated functions are also reported.