An evolutionary algorithm for reducing integrated-circuit test application time
Proceedings of the 2002 ACM symposium on Applied computing
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
ARPIA: A High-Level Evolutionary Test Signal Generator
Proceedings of the EvoWorkshops on Applications of Evolutionary Computing
Advanced Techniques for GA-based sequential ATPGs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Empirical studies of the genetic algorithm with noncoding segments
Evolutionary Computation
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Reducing production-test application time is a key problem for modern industries. Several different hardware solutions have been proposed in the literature to ease such process. However, each hardware architecture must be coupled with an effective test signals generation algorithm. This paper propose an evolutionary approach for minimizing the application time of a test set by opportunely extending it and exploiting a new hardware architecture, named interleaved scan. The peculiarities of the problem suggest the use of a slightly modified genetic algorithm with concurrent populations. Experimental results show the effectiveness of the approach against the traditional ones.