An evolutionary algorithm for reducing integrated-circuit test application time

Authors:
F. Corno;M. Sonza Reorda;G. Squillero
Affiliations:
Politecnico di Torino, Cso Duca degli Abruzzi 24, 10129 Torino --- Italy;Politecnico di Torino, Cso Duca degli Abruzzi 24, 10129 Torino --- Italy;Politecnico di Torino, Cso Duca degli Abruzzi 24, 10129 Torino --- Italy
Venue:
Proceedings of the 2002 ACM symposium on Applied computing
Year:
2002

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Abstract

The cost for testing integrated circuits represents a growing percentage of the total cost for their production. The former strictly depends on the length of the test session, and its reduction has been the target of many efforts in the past. This paper proposes a new method for reducing the test length by adopting a new architecture and exploiting an evolutionary optimization algorithm. A prototype of the proposed approach was tested on ISCAS standard benchmarks and the experimental results show its effectiveness.