Floor-planning by graph dualization: 2-concave rectilinear modules
SIAM Journal on Computing
DAC '93 Proceedings of the 30th international Design Automation Conference
A unified approach to topology generation and area optimization of general floorplans
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Rectilinear block placement using sequence-pair
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Topology constrained rectilinear block packing for layout reuse
ISPD '98 Proceedings of the 1998 international symposium on Physical design
A Minimum-Area Floorplanning Algorithm for MBC Designs
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Module packing based on the BSG-structure and IC layout applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Constrained "Modern" Floorplanning
Proceedings of the 2003 international symposium on Physical design
A novel thermal optimization flow using incremental floorplanning for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Full Length Article: 3D thermal-aware floorplanner using a MILP approximation
Microprocessors & Microsystems
3D thermal-aware floorplanner using a MOEA approximation
Integration, the VLSI Journal
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A productivity-driven methodology for incremental floorplanning is described and the constrained polygon transformation problem, a key step of this methodology, is formulated. The input to the problem consists of a floorplan computed using area estimates and the actual area required for each subcircuit of the floorplan. Informally, the objective is to change the areas of the modules without drastically changing their shapes or locations. We show that the constrained polygon transformation problem is NP-hard and present several fast algorithms that produce results within a few percent of a theoretical lower bound on several floorplans.