BSG-Route: a length-matching router for general topology
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Theories and algorithms on single-detour routing for untangling twisted bus
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Exact route matching algorithms for analog and mixed signal integrated circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
BSG-route: a length-constrained routing scheme for general planar topology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Two-sided single-detour untangling for bus routing
Proceedings of the 47th Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Obstacle-aware longest path using rectangular pattern detouring in routing grids
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Obstacle-aware length-matching bus routing
Proceedings of the 2011 international symposium on Physical design
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
Maze routing algorithms with exact matching constraints for analog and mixed signal designs
Proceedings of the International Conference on Computer-Aided Design
Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits
Proceedings of the 50th Annual Design Automation Conference
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As the clock frequencies used in industrial applications increase, the timing requirements on routing problems become tighter, and current routing tools cannot successfully handle these constraints any more. In this paper, the authors focus on the high-performance single-layer bus routing problem, where the objective is to match the lengths of all nets belonging to each bus. An effective approach to solve this problem is to allocate extra routing resources around short nets during routing, and use those resources for length extension afterwards. First, a provably optimal algorithm for routing nets with minimum-area maximum-length constraints is proposed. Then, this algorithm is extended to the case where minimum constraints are given as exact length bounds, and it is also proven that this algorithm is near-optimal. Both algorithms proposed are shown to be scalable for large circuits, since the respective time complexities are O(A) and O(AlogA), where A is the area of the intermediate region between chips.