Self-reforming routing for stochastic search in VLSI interconnection layout
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Introduction to Algorithms
BSG-Route: a length-matching router for general topology
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Two-sided single-detour untangling for bus routing
Proceedings of the 47th Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Obstacle-aware longest path using rectangular pattern detouring in routing grids
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Algorithmic study of single-layer bus routing for high-speed boards
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.01 |
As clock frequency increases, signal propagation delay on PCBs is requested to meet the timing specification with very high accuracy. Generally speaking, the net length in a single layer can estimate the routing delay in a single-layer net. In this paper, given a set of r single-layer nets in a bus with their length constraints inside mxn routing grids with s obstacle grids, based on obstacle-aware region partition inside routing grids, obstacle-aware shortest path generation and two detouring operations, R-flip and C-flip, an efficient O(mn+s3) algorithm is proposed to generate the length-matching paths for obstacle-aware bus routing. Compared with the published CAFE router, our proposed routing algorithm can save 80.5% of CPU time to complete obstacle-aware length-matching bus routing with no length error for tested examples on the average.