Escape routing for dense pin clusters in integrated circuits
Proceedings of the 44th annual Design Automation Conference
Archer: a history-driven global routing algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BSG-Route: a length-matching router for general topology
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Theories and algorithms on single-detour routing for untangling twisted bus
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Detailed-routing algorithms for dense pin clusters in integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Archer: a history-based global routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact route matching algorithms for analog and mixed signal integrated circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
Optimal layer assignment for escape routing of buses
Proceedings of the 2009 International Conference on Computer-Aided Design
BSG-route: a length-constrained routing scheme for general planar topology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Two-sided single-detour untangling for bus routing
Proceedings of the 47th Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Obstacle-aware longest path using rectangular pattern detouring in routing grids
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Obstacle-aware length-matching bus routing
Proceedings of the 2011 international symposium on Physical design
New optimal layer assignment for bus-oriented escape routing
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
New optimal layer assignment for bus-oriented escape routing
Integration, the VLSI Journal
Maze routing algorithms with exact matching constraints for analog and mixed signal designs
Proceedings of the International Conference on Computer-Aided Design
Post-route refinement for high-frequency PCBs considering meander segment alleviation
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits
Proceedings of the 50th Annual Design Automation Conference
Post-route alleviation of dense meander segments in high-performance printed circuit boards
Proceedings of the International Conference on Computer-Aided Design
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As the clock frequencies used in industrial applications increase, the timing requirements imposed on routing problems become tighter. Therefore, it becomes important to route the nets within tight minimum and maximum length bounds. Although the problem of routing nets to satisfy maximum length constraints is a well-studied problem, there exists no sophisticated algorithm in literature that ensures that minimum length constraints are also satisfied. In this paper, the authors propose a novel algorithm that effectively incorporates the min;max length constraints into the routing problem. The approach is to use a Lagrangian-relaxation (LR) framework to allocate extra routing resources around nets simultaneously during routing them. The authors also propose a graph model that ensures that all the allocated routing resources can be used effectively for extending lengths. Their routing algorithm automatically prioritizes resource allocation for shorter nets and length minimization for longer nets so that all nets can satisfy their min;max length constraints. This paper demonstrates that this algorithm is effective even in the cases where length constraints are tight, and the spacing between adjacent nets is small