System-level routing of mixed-signal ASICs in WREN
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Two-layer bus routing for high-speed printed circuit boards
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BSG-Route: a length-matching router for general topology
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Exact route matching algorithms for analog and mixed signal integrated circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
Algorithmic study of single-layer bus routing for high-speed boards
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous analog placement and routing with current flow and current density considerations
Proceedings of the 50th Annual Design Automation Conference
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Design automation for analog and mixed signal designs has become more important, as analog and digital components are integrated on the same system-on-chips (SOCs). Exact route matching is an important constraint for analog and mixed signal designs with non-uniform metal stacks. In this paper, we propose a constrained-path based maze routing algorithm that can handle exact matching constraints for multiple nets. We also propose a scalable framework that utilizes the proposed maze routing algorithm for realistic problem sizes. Compared to the pattern routing algorithms proposed recently [8], our algorithms allow a more thorough exploration of the solution space by allowing bends to be inserted to avoid congested regions. The experimental study demonstrates that the proposed algorithm leads to significant reductions in congestion costs compared to the previous algorithm.