Area-I/O flip-chip routing for chip-package co-design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
3D Stacked Package Technology and Its Application Prospects
NISS '09 Proceedings of the 2009 International Conference on New Trends in Information and Service Science
Recent research development in flip-chip routing
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 2.88 |
The through silicon via (TSV) is a technology for vertical interconnection between multiple chips that employ a hole bored through a Si wafer and stack chips, which is good for securing a number of I/O per unit area reducing the electric resistance. On the other hand, vertical multi-layers are structurally more unstable than a single-layer but are vulnerable to a thermo-mechanical effect. Therefore, in this study, finite element analysis (FEA) of a three-dimensional (3D) multi-layer semiconductor with TSV was carried out to examine the changes in thermo-mechanical stress at the bonding interface with different models of Cu pillar bumps and Sn-3.5Ag solder bumps. A numerical simulation was carried out with different models, such as a plate type, pin type, skirt type, zigzag type and conical frustum type. The height and diameter of each solder bump were 10@mm and 30@mm, respectively. The distribution of Von Mises stress occurred more at the solder joint interface and TSV joint interface. At the solder joint interface, the stress in the skirt type (100.6MPa) was approximately double that in the conical frustum type (53.1MPa). At the TSV joint interface, the stress in the plate type (17.2MPa) was higher than that in the other types. The stress values were similar in the other types except for plate type Cu pillar bump. Stress in the solder and TSV joint interface was caused partly by the difference in properties between the two materials. In particular, mismatch in the coefficient of thermal expansion (CTE) had the greatest effect on the stress distribution.