I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os

Authors:
James P. Libous
Affiliations:
-
Venue:
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Year:
2001

Citing 0
Cited 2

Design migration from peripheral ASIC design to area-I/O flip-chip design by chip I/O planning and legalization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-in-Package: Electrical and Layout Perspectives

Foundations and Trends in Electronic Design Automation

Quantified Score

Hi-index	0.00

Visualization

Abstract

Optimized I/O cell placement techniques take into account electromigration (EM), IR drop, and dI/dt noise issues in the power distribution network. This paper describes fast and easy electrical checking algorithms to be used early in the design process to verify if the I/O placements meet placement guidelines, and explains the details of the I/O cell placement-related rules used by the checking tool. Use of these techniques and methods can ensure high quality ASICs.