Signal Attenuation in Transmission Lines
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
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Recent advances in microprocessor technology require high-speed, high performance, and high-pincount devices. With a large number of simultaneous switching drivers at frequencies in excess of 100MHz and large numbers of core logic transistors switching at frequencies in excess of 350MHz in the microprocessor, the problem of matching a package to the microprocessor's drivers & core logic requirements to the environment of a low cost motherboard becomes a real challenge. In addition to having high speed input/output signals, microprocessors designed for low power consumption (~2volts), require the package to provide a low inductance path between the drivers, the decoupling capacitors, and the motherboard. This paper will show how different package stackups, number of power and ground planes, and the number of routing layers affect the performance of the packaging device and subsequently the current consumption demanded by the simultaneously switching drivers and core logic on the microprocessor. A multilayer ceramic package with solid planes and thin substrates will be analyzed to provide a complete characterization of the system made of drivers, core logic, package, and motherboard. Such analysis serves as a basic building block for setting a criteria on different package designs.An electrical model, based on state-of-the art software tools, will be presented. The model is used for extracting advantages and performance characteristics of package stackups and routing layers on ceramic pin grid array (CPGA) and ceramic ball grid array (CBGA) packages. Driver models and an electrical model for the motherboard are also combined together with the package models to show the effectiveness of packages on performance of a microprocessor.