Enhancing timing-driven FPGA placement for pipelined netlists

Authors:
Ken Eguro;Scott Hauck
Affiliations:
University of Washington, Seattle, WA;University of Washington, Seattle, WA
Venue:
Proceedings of the 45th annual Design Automation Conference
Year:
2008

Citing 3
Cited 2

PathFinder: a negotiation-based performance-driven router for FPGAs

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Timing-driven placement for FPGAs

FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Armada: timing-driven pipeline-aware routing for FPGAs

Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

Improving FPGA placement with dynamically adaptive stochastic tunneling

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scalable and deterministic timing-driven parallel placement for FPGAs

Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays

Quantified Score

Hi-index	0.00

Visualization

Abstract

FPGA application developers often use pipelining, C-slowing and retiming to improve the performance of their designs. Unfortunately, registered netlists present a fundamentally different problem to CAD tools, potentially limiting the benefit of these techniques. In this paper we discuss some of the inherent issues pipelined netlists pose to existing timing-driven placement approaches. We then present two algorithmic modifications that reduce post-routing critical path delay by an average of 40%.