PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Layout decomposition for double patterning lithography
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning technology friendly detailed routing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
GREMA: graph reduction based efficient mask assignment for double patterning technology
Proceedings of the 2009 International Conference on Computer-Aided Design
Double patterning lithography aware gridless detailed routing with innovative conflict graph
Proceedings of the 47th Design Automation Conference
Post-routing layer assignment for double patterning
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Layout decomposition for triple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Optimal layout decomposition for double patterning technology
Proceedings of the International Conference on Computer-Aided Design
Dealing with IC manufacturability in extreme scaling
Proceedings of the International Conference on Computer-Aided Design
An efficient layout decomposition approach for triple patterning lithography
Proceedings of the 50th Annual Design Automation Conference
A high-performance triple patterning layout decomposer with balanced density
Proceedings of the International Conference on Computer-Aided Design
Constrained pattern assignment for standard cell based triple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Methodology for standard cell compliance and detailed placement for triple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
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As technology continues to scale to 14nm node, Double Patterning Lithography (DPL) is pushed to near its limit. Triple Patterning Lithography (TPL) is a considerable and natural extension along the paradigm of DPL. With an extra mask to accommodate the features, TPL can be used to eliminate the unresolvable conflicts and minimize the number of stitches, which are pervasive in DPL process, and thus smoothen the layout decomposition step. Considering TPL during routing stage explores a larger solution space and can further improve the layout decomposability. In this paper, we propose the first triple patterning aware detailed routing scheme, and compare its performance with the double patterning version in 14nm node. Experimental results show that, using TPL, the conflicts can be resolved much more easily and the stitches can be significantly reduced in contrast to DPL.