JITPR: A framework for supporting fast application's implementation onto FPGAs

Authors:
Harry Sidiropoulos;Kostas Siozios;Peter Figuli;Dimitrios Soudris;Michael Hübner;Jürgen Becker
Affiliations:
National Technical University of Athens, Greece;National Technical University of Athens, Greece;Karlsruhe Institute of Technology, Karlsruhe, Germany;National Technical University of Athens, Greece;Ruhr-University of Bochum, Germany;Karlsruhe Institute of Technology, Karlsruhe, Germany
Venue:
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
Year:
2013

Citing 9
Cited 0

PathFinder: a negotiation-based performance-driven router for FPGAs

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Fast placement approaches for FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Architecture and CAD for Deep-Submicron FPGAs

Architecture and CAD for Deep-Submicron FPGAs
Bitstream relocation with local clock domains for partially reconfigurable FPGAs

Proceedings of the Conference on Design, Automation and Test in Europe
A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture

IPDPSW '11 Proceedings of the 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum
Reducing FPGA Router Run-Time through Algorithm and Architecture

FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
A fast discrete placement algorithm for FPGAs

Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation

IPDPSW '12 Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum
On supporting rapid exploration of memory hierarchies onto FPGAs

Journal of Systems Architecture: the EUROMICRO Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

The execution runtime usually is a headache for designers performing application mapping onto reconfigurable architectures. In this article we propose a methodology, as well as the supporting toolset, targeting to provide fast application implementation onto reconfigurable architectures with the usage of a Just-In-Time (JIT) compilation framework. Experimental results prove the efficiency of the introduced framework, as we reduce the execution runtime compared to the state-of-the-art approach on average by 53.5×. Additionally, the derived solutions achieve higher operation frequencies by 1.17×, while they also exhibit significant lower fragmentation ratios of hardware resources.