Using simulated annealing to design good codes
IEEE Transactions on Information Theory
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Performance-driven mapping for CPLD architectures
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Architectures and algorithms for synthesizable embedded programmable logic cores
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Design of Interconnection Networks for Programmable Logic
Design of Interconnection Networks for Programmable Logic
Automating the Layout of Reconfigurable Subsystems Via Template Reduction
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
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Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurability, or even be used for post-fabrication modifications. Also, by tailoring the logic to the SoC domain, additional area and delay gains can be achieved over current, more general reconfigurable fabrics. This paper presents our work on creating efficient CPLD architectures for SoC, including the creation of sparse crossbars, and a novel switch smoothing algorithm which makes the crossbars amenable to layout. For our largest architecture, the switch smoothing algorithm reduced the layout's wire jog pitch from 48 to just 3, allowing for a compact VLSI layout. This has helped pave the way for our sparse-crossbar based CPLDs, which require just .37x the area and .30x the delay of our full-crossbar based CPLDs.However, regardless of how efficient an architecture we develop, it is useless if it does not have enough resources to support the circuits to be implemented. We also address the question of how best to add resources to a CPLD in order to support future, unknown circuits, concluding that the best strategy is to add 5% to the crossbar switch density and to provide additional PLAs of the same size found in the base architecture.