Incremental capacitance extraction and its application to iterative timing-driven detailed routing
ISPD '99 Proceedings of the 1999 international symposium on Physical design
An architecture-driven metric for simultaneous placement and global routing for FPGAs
Proceedings of the 37th Annual Design Automation Conference
Timing-driven routing for symmetrical array-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In segmented channel routing of row-based FPGA's, the routability and interconnection delays depend on the choice of upper bounds on the number of programmable switches allocated for routing net segments in the channel. Traditionally, the upper bounds for the net segments in the same channel are set uniformly. In this paper, we present algorithms for determining the upper bounds for all of the net segments of a net simultaneously, so that the predefined source-to-sink delay bound on the net is satisfied and the routability of the net is maximized. The upper bounds on net segments in a channel determined by the algorithms in general are nonuniform. Experimental results show that the algorithms can significantly improve routability and reduce delay bound violation as compared with the traditional, uniform upper bound approach