Chortle: a technology mapping program for lookup table-based field programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Chortle-crf: Fast technology mapping for lookup table-based FPGAs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Routable Technologie Mapping for LUT FPGAs
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Notes on “Complexity of the lookup-table minimization problem for FPGA technology mapping”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a polynomial time algorithm which can run in O(n3) time to generate an efficient solution where n is the total number of gates in the circuit. The proposed algorithm partitions the graph representing the given circuit into subgraphs such that the solution can be obtained by merging the subgraph solutions. The greedy technique is then used to find the solution for each subgraph. It is shown that except for some cases the greedy method can find an optimal solution of a given problem. We have tested our algorithm on a set of benchmark examples. The experimental results demonstrate the effectiveness of our algorithm.