Integer and combinatorial optimization
Integer and combinatorial optimization
Logic synthesis for programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Chortle-crf: Fast technology mapping for lookup table-based FPGAs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An improved synthesis algorithm for multiplexor-based PGA's
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On area/depth trade-off in LUT-based FPGA technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
High-level test generation using physically-induced faults
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
General modeling and technology-mapping technique for LUT-based FPGAs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
A general approach for regularity extraction in datapath circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells
ACM Transactions on Design Automation of Electronic Systems (TODAES)
General technology mapping for field-programmable gate arrays based on lookup tables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Effective and efficient FPGA synthesis through general functional decomposition
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
An efficient algorithm for finding the minimal-area FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
| Hi-index | 0.00 |
We show that the FPGA technology mapping problem can be efficiently implemented as a mixed integer linear programming (MILP) problem which generates truly optimal mappings. The MILP approach can handle a wide variety of FPGA logic block architectures. We present a compact MILP formulation for logic blocks based on lookup tables (LUTs) multiplexers. We also show that the MILP formulation can be easily modified to modified to optimize area, delay, or a combination of both. We demonstrate that moderately large benchmark circuits can be mapped in a reasonable time using the MILP approach directly. For larger circuits, we propose a technique of partitioning a circuit prior to mapping, which drastically reduces the computation time with little or no loss in optimality.