Using if-then-else DAGs for multi-level logic minimization
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Logic synthesis for programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
DAC '97 Proceedings of the 34th annual Design Automation Conference
The disjunctive decomposition of logic functions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient state representation for symbolic simulation
Proceedings of the 39th annual Design Automation Conference
Layout Driven Decomposition with Congestion Consideration
Proceedings of the conference on Design, automation and test in Europe
USING IF-THEN-ELSE DAGS TO DO TECHNOLOGY MAPPING FOR FIELD-PROGRAMMABLE GATE ARRAYS
USING IF-THEN-ELSE DAGS TO DO TECHNOLOGY MAPPING FOR FIELD-PROGRAMMABLE GATE ARRAYS
Achieving scalable hardware verification with symbolic simulation
Achieving scalable hardware verification with symbolic simulation
OBDD-based function decomposition: algorithms and implementation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Smart Enumeration: A Systematic Approach to Exhaustive Search
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition
Proceedings of the 50th Annual Design Automation Conference
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A disjoint support decomposition (DSD) is a representation of a Boolean function F obtained by composing two or more simpler component functions such that the component functions have no common inputs. The decomposition of a function is desirable for several reasons. First, it's a method to obtain a multiple-level implementation of a function. It leads to a partition in simpler blocks that easily results in smaller areas and fewer interconnects. Moreover, it exposes a parallelism in the computation of the function that can be exploited by hardware as well as during simulation.In this paper we present a novel algorithm, STACCATO, that generates a DSD decomposition starting from the BDD of a function. STACCATO is novel because 1) it provides a complete description of each decomposition, that is, it computes the "kernel" function K relating the elements of each decomposition, and 2) it has better performance than previously known algorithms. Experimental results run on both IWLS and industrial test-benches show that STACCATO's performance is in most cases three times as fast or more than previously known solutions.