Wafer-Scale Integration Using Restructurable VLSI
Computer - Special issue on wafer-scale integration
On Routability for FPGAs under Faulty Conditions
IEEE Transactions on Computers
The Teramac Custom Computer: Extending the Limits with Defect Tolerance
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
| Hi-index | 0.00 |
Chip defect densities set the complexity limits of FPGAs. However, wafer-scale techniques expand this with defect avoidance routing around flawed blocks to build working systems. FPGAs have the features required for successful defect avoidance systems: repeatable cells, built-in switchable flexible routing, and potentially large number of applications. Laser-formed connections/cuts switches are effective in bypassing fabrication time defects in cell power, clocks, and signal buses, thus creating defect-free large working systems. Experiments on test FPGAs show laser defect avoidance routing signal delays 50% those of active switches. Thus laser defect avoidance after fabrication eliminates errors creating large-area FPGAs whose defective cell distribution is nearly unseen by the user.