Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
A CAD system for the design of field programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Plane parallel a maze router and its application to FPGAs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Switch bound allocation for maximizing routability in timing-driven routing of FPGAs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Performance-driven simultaneous place and route for row-based FPGAs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Testing of uncustomized segmented channel field programmable gate arrays
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Effects of FPGA architecture on FPGA routing
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
FPGA routing and routability estimation via Boolean satisfiability
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Architectural and physical design challenges for one-million gate FPGAs and beyond
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Architecture and routability analysis for row-based FPGAs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Switch module design with application to two-dimensional segmentation design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
New channel segmentation model and associated routing algorithm for high performance FPGAs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
On channel segmentation design for row-based FPGAs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Efficient routability check algorithms for segmented channel routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On Routability for FPGAs under Faulty Conditions
IEEE Transactions on Computers
Genetic Programming and Evolvable Machines
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Slotless module-based reconfiguration of embedded FPGAs
ACM Transactions on Embedded Computing Systems (TECS)
| Hi-index | 0.00 |
Routing channels in a field-programmable gate array contain predefined wiring segments of various lengths. These may be connected to the pins of the gates or joined end-to-end to form longer segments by programmable switches. The segmented channel routing problem is formulated, and polynomial time algorithms are given for certain special cases. The general problem is NP-complete, but it can be adequately solved in practice. Experiments indicate that a segmented channel with judiciously chosen segment lengths may near the efficiency of a conventional channel.