Reliable computer systems (2nd ed.): design and evaluation
Reliable computer systems (2nd ed.): design and evaluation
Architecture issues and solutions for a high-capacity FPGA
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
On Routability for FPGAs under Faulty Conditions
IEEE Transactions on Computers
Defect Tolerant SRAM Based FPGAs
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
An approach for testing programmable/configurable field programmable gate arrays
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On Modifying Logic Networks to Improve Their Diagnosability
IEEE Transactions on Computers
A study of the data commutation problems in a self-repairable multiprocessor
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
Efficiently supporting fault-tolerance in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
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We propose a technique for online built-in self-test of Field Programmable Gate Arrays (FPGAs). The goal of this system is to detect deviations from the intended functionality of an FPGA without using special-purpose hardware, hardware external to the device, and without interrupting system operation. A system that solves these problems would be useful for mission-critical applications with resource constraints. We present here a fault detection system which solves these problems through an online fault scanning methodology. Resources internal to the device are configured to test for faults. Testing scans across an FPGA, checking a section at a time. The viability and effectiveness of such a system is supported through simulation of the system on a model FPGA.