Easily Testable Iterative Systems
IEEE Transactions on Computers
A Nand Model ror Fault Diagnosis in Combinational Logic Networks
IEEE Transactions on Computers
On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests
IEEE Transactions on Computers
Derivation of optimum test sequencies for sequential machines
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
Fault Scanner for Reconfigurable Logic
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Speculation on the future of design automation
DAC '74 Proceedings of the 11th Design Automation Workshop
Design of Totally Fault Locatable Combinational Networks
IEEE Transactions on Computers
Design for Testability A Survey
IEEE Transactions on Computers
Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays
IEEE Transactions on Computers
On Minimally Testable Logic Networks
IEEE Transactions on Computers
The Complexity of Fault Detection Problems for Combinational Logic Circuits
IEEE Transactions on Computers
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This paper considers the use of control logic to reduce the number of tests required by a logic network and to simplify test generation. The properties of EXCLUSIVE-OR (EOR) circuits as control elements are examined. Systematic procedures are presented for modifying any combinational or sequential network so that the resulting network requires only five tests. These tests can easily be generated using a set of predefined test patterns of length five. The design of diagnosable networks using a limited amount of control logic is also discussed.