Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
A Fault Tolerant Technique for FPGAs
Journal of Electronic Testing: Theory and Applications
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Analysing evolvable cell design for optimisation of routing options
Proceedings of the 9th annual conference companion on Genetic and evolutionary computation
Online fault tolerance for FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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REMOD (REprocessing with MicrO Delays) is a new method for fault-tolerant design of logic circuits composed of arrays of identical functional cells. The fault detection scheme is based on the principle of node covering, in which the computation of each cell is checked by a "covering" cell. After a faulty cell is detected, the node covering principle also allows the circuit to easily be reconfigured to perform correctly for subsequent inputs. Furthermore, the design method is extendable to multiple fault tolerance with only small increments of hardware and time. We have laid out and simulated REMOD-based circuits for adders and multipliers and show that the time overheads are a small factor of the original computation time-0 or /spl Theta/(1/n) to /spl Theta/(1/(log n)), for an n-cell circuit. For moderately complex cells, it is seen that area overhead is very reasonable as well.