Barrier and seed layer coverage in 3D structures with different aspect ratios using sputtering and ALD processes

  • Authors:

  • O. Lühn;C. Van Hoof;W. Ruythooren;J. -P. Celis

  • Affiliations:

  • Interuniversity Microelectronics Center (IMEC), Kapeldreef 75, 3001 Leuven, Belgium and Katholieke Universiteit Leuven, Department of MTM, Kasteelpark Arenberg 44, 3001 Leuven, Belgium;Interuniversity Microelectronics Center (IMEC), Kapeldreef 75, 3001 Leuven, Belgium and Katholieke Universiteit Leuven, Department of ESAT, Kasteelpark Arenberg 10, 3001 Leuven, Belgium;Interuniversity Microelectronics Center (IMEC), Kapeldreef 75, 3001 Leuven, Belgium;Katholieke Universiteit Leuven, Department of MTM, Kasteelpark Arenberg 44, 3001 Leuven, Belgium

  • Venue:
  • Microelectronic Engineering
  • Year:
  • 2008

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Abstract

Established technologies for the deposition of barrier layers and seed layers for 3D interconnect technology were investigated for their limits of obtaining a continuous and conductive layer in 3D structures. Sputtering, and sputtering coupled with a self-ionized plasma as well as atomic layer deposition, in combination with direct-on-barrier electroplating were used. The diameter of the investigated vias and trenches was scaled from 100 to 5@mm with depths down to 360@mm, covering a large range of aspect ratio up to 29. The deposition technologies were investigated and evaluated by analyzing cross-sections of coated vias with optical microscopy, scanning electron microscopy, and focused ion beam. An aspect ratio technology map is presented that shows the limits of the investigated coating technologies to achieve a continuous conductive surface layer on the wall and bottom of vias and trenches of various aspect ratios. Vias and trenches were successfully coated with a continuous barrier and a copper seed offering electrical continuity for aspect ratios up to 29.