Bottom-up copper electroplating using transfer wafers for fabrication of high aspect-ratio through-silicon-vias

Authors:
Chongshen Song;Zheyao Wang;Litian Liu
Affiliations:
Institute of Microelectronics, Tsinghua University, Beijing 100084, China;Institute of Microelectronics, Tsinghua University, Beijing 100084, China;Institute of Microelectronics, Tsinghua University, Beijing 100084, China
Venue:
Microelectronic Engineering
Year:
2010

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Abstract

Three-dimensional (3D) integration is emerging as an attractive technology to continue Moore's law through the integration of multi-stacked chips interconnected with through-silicon-vias (TSVs). To address the challenge in filling high aspect-ratio TSVs with copper, this paper reports an improved bottom-up copper electroplating (BCE) technique by introducing a glass transfer wafer, which is temporarily bonded with the device wafer to provide a copper seed layer. As the copper seed layer on the transfer wafer covers the through-holes, copper is electroplated from the bottom seed layer to the top opening of the through-holes without forming any voids or seams. This avoids the time consuming sealing process in conventional BCE, which normally takes 3-5h. Thanks to the mechanical support of the transfer wafer, the device wafer can be thinned to several tens of micrometers. Using this technique, TSVs with diameter of 5@mm and aspect-ratio of 13:1 have been achieved. Based on the improved BCE technique, a through-via type 3D integration strategy is developed.