Damascene Copper electroplating for chip interconnections

  • Authors:
  • P. C. Andricacos;C. Uzoh;J. O. Dukovic;J. Horkans;H. Deligianni

  • Affiliations:
  • IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Microelectronics Division, East Fishkill facility, Route 52, Hopewell Junction, New York;IBM Research Divsion, Thomas J. Watson Research Center, P. O. Box 218, Yorktown Heights, New York;IBM Research Divsion, Thomas J. Watson Research Center, P. O. Box 218, Yorktown Heights, New York;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York

  • Venue:
  • IBM Journal of Research and Development - Electrochemical microfabrication
  • Year:
  • 1998

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Abstract

Damascene Cu electroplating for on-chip metallization, which we conceived and developed in the early 1990s, has been central to IBM's Cu chip interconnection technology. We review here the challenges of filling trenches and vias with Cu without creating a void or seam, and the discovery that electrodeposition can be engineered to give filling performance significantly better than that achievable with conformal step coverage. This attribute of superconformal deposition, which we call superfilling, and its relation to plating additives are discussed, and we present a numerical model that represents the shape-change behavior of this system.