VLSI on-chip interconnection performance simulations and measurements
IBM Journal of Research and Development
The chemistry of additives in damascene copper plating
IBM Journal of Research and Development - Electrochemical technology in microelectronics
Design and modeling of equipment used in electrochemical processes for microelectronics
IBM Journal of Research and Development - Electrochemical technology in microelectronics
High aspect ratio copper through-silicon-vias for 3D integration
Microelectronic Engineering
Microelectronic Engineering
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Damascene Cu electroplating for on-chip metallization, which we conceived and developed in the early 1990s, has been central to IBM's Cu chip interconnection technology. We review here the challenges of filling trenches and vias with Cu without creating a void or seam, and the discovery that electrodeposition can be engineered to give filling performance significantly better than that achievable with conformal step coverage. This attribute of superconformal deposition, which we call superfilling, and its relation to plating additives are discussed, and we present a numerical model that represents the shape-change behavior of this system.