3-D stacked CMOS inverters using Pt/HfO2 on Si substrate for vertical integrated CMOS applications

  • Authors:

  • Soon-Young Oh;Chang-Geun Ahn;Jong-Heon Yang;Won-Ju Cho;Moon-Gyu Jang

  • Affiliations:

  • Nano-Bio Electronic Devices Team, Electronics and Telecommunications Research Institute, 161 Gajeong-Dong, Yuseong-Gu, Daejeon 305-350, Republic of Korea;Nano-Bio Electronic Devices Team, Electronics and Telecommunications Research Institute, 161 Gajeong-Dong, Yuseong-Gu, Daejeon 305-350, Republic of Korea;Nano-Bio Electronic Devices Team, Electronics and Telecommunications Research Institute, 161 Gajeong-Dong, Yuseong-Gu, Daejeon 305-350, Republic of Korea;Electronic Materials, Kwangwoon University, 447-1 Wolgye-Dong, Nowon-Gu, Seoul 139-701, Republic of Korea;Nano-Bio Electronic Devices Team, Electronics and Telecommunications Research Institute, 161 Gajeong-Dong, Yuseong-Gu, Daejeon 305-350, Republic of Korea

  • Venue:
  • Microelectronic Engineering
  • Year:
  • 2008

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Abstract

Three-dimensionally stacked CMOS inverters were fabricated by using the poly-Si thin film transistor (TFT) with hafnium-oxide (HfO"2) gate dielectric and Pt gate electrode. For fabrication of 3-D stacked CMOS inverters consist of poly-Si NMOS/interlayer dielectric film (ILD)/poly-Si PMOS, a reduced process temperature is necessary to avoid the degradation of NMOS at lower poly-Si layer fabricated prior to PMOS at upper poly-Si layer. The high quality of laser crystallized poly-Si film was obtained with smooth surface and excellent crystallinity. The 3-D stacked CMOS inverters fabricated by stacking the poly-Si NMOS TFT and PMOS TFT showed good output characteristics, DC voltage transfer characteristics, transient characteristics and voltage gain for applications of the vertical integrated CMOS circuits.