Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Strategies for improving the parametric yield and profits of 3D ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Maximizing the functional yield of wafer-to-wafer 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Process-induced skew variation for scaled 2-D and 3-D ICs
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
An industrial perspective of 3D IC integration technology: from the viewpoint of design technology
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Homogeneous integration for 3D IC with TSV
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Effect of process variations in 3D global clock distribution networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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This paper examines the ramifications of using 3D integration technology on the leakage and timing variability of integrated circuits. We develop models that estimate the outcome of mapping a 2D design onto a 3D stack from a process variation perspective. We statistically prove and experimentally demonstrate that 3D integration is a useful technique to combat process variations even if the die/wafers layers involved in 3D stacks are integrated blindly without any parametric tests prior to integration. We further show that if individual die parametric testing information is available, then it is possible to drastically reduce the impact of process variations. We develop fast, near optimal integration strategies based on recursive matching techniques. Our results show that 3D integration can reduce the variability in leakage and timing of planar ICs by around 50% without any testing and by more than 90% with additional test requirements.