System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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Proceedings of the Conference on Design, Automation and Test in Europe
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Proceedings of the Conference on Design, Automation and Test in Europe
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DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Microelectronic wafer and die level testing have undergone significant changes in the past few years. This paper's first section describes today's leading edge characteristics for numerous areas of this test technology including the minimum I/O pad pitch, advances in contactor technologies, maximum number of I/Os probed, maximum number of die tested in parallel, the largest prober and substrates, and the maximum frequencies being tested at the wafer level. The second section will discuss the leading edge practices in three critical areas of wafer test: probe contactor cleaning, I/O pad damage minimization, and sorting good from bad die. The final section will present the communication methods between the design and the probe test organizations and some state-of-the-art examples for I/O pad designs..