Compressionless Routing: A Framework for Adaptive and Fault-Tolerant Routing
IEEE Transactions on Parallel and Distributed Systems
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Introduction to Algorithms
Scouting: Fully Adaptive, Deadlock-Free Routing in Faulty Pipelined Networks
Proceedings of the 1994 International Conference on Parallel and Distributed Systems
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
THE LEADING EDGE OF PRODUCTION WAFER PROBE TEST TECHNOLOGY
ITC '04 Proceedings of the International Test Conference on International Test Conference
Data Structures and Problem Solving Using C++ (3rd Edition)
Data Structures and Problem Solving Using C++ (3rd Edition)
Broadcasting and routing in faulty mesh networks
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Diagnosis of clustered faults and wafer testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diagnosis of clustered faults for identical degree topologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 3rd International Conference on Future Energy Systems: Where Energy, Computing and Communication Meet
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A novel DFT approach is introduced that enables massively parallel testing of logic devices at both wafer and package test. Parallelism is achieved by utilizing interconnection networks that are built onto a wafer probe or a tester interface unit. The financial benefits of this method in a realistic setting are also presented.