Nanometer Design: What are the Requirements for Manufacturing Test?

• Authors: Janusz Rajski;Kan Thapar
• Venue: Proceedings of the conference on Design, automation and test in Europe - Volume 2
• Year: 2004

Why is nanometer technology different from any other previous smaller geometry process? Why should the requirements for manufacturing test be dissimilar to what we have had until now? In the past, most test challenges paralleled the device transistor count and Moore's Lawof device complexity was a good predictor of their magnitude.Nanometer technology is affecting test in several new significant ways. Complex copper interconnects, low-k dielectric materials, continued transistor scaling, and new manufacturing processes are completely changing defect distributions. There are more node-to-node bridges undetected by tests for stuck-at faults, more node-to-node resistive bridges that require at-speed test, more in-line resistances caused by defective vias, and more cross-talk effects undetected by Iddq tests. Numerous small delay defects are detected only when they propagate to outputs with a small slack.In addition to traditional defects, in nanometer technology, circuits often malfunction as a result of design and process marginalities that increase delay sensitivity, noise sensitivity and manifest themselves as cross talk and IR drop effects. Even though those are not the traditional defects these types of malfunctions have to be detected and diagnosed through test techniques. The transistor scaling rules that define optimal performance require that, with reduced transistor gate length, both the voltage and gate oxide are reduced as well. That in turn increases leakage current and diminishes effectiveness of Iddq test. More fragile transistors also impose restrictions on reliability screening such as burn-in test.Nanometer technology enables manufacturing of very large SoC designs that have many cores originating from a variety of sources. The challenge here is to integrate different test solutions provided by suppliers of those cores into one comprehensive chip level test. Eventhough the designs are bigger and more difficult to test, one of the principal requirements is to reduce the cost of manufacturing test.This panel, comprised of the industry experts, will debate the requirements for manufacturing test for nanometer technology designs. In particular, the panel will address the following topics.What are the requirements for high quality test?New types of defects that should be targeted.Most significant design and process marginalities.The biggest new constraints impacting test.Requirements for new DFT methodologies supporting high-quality low-cost manufacturing test.Other requirements for efficient manufacturing test.Requirements for reliability screening.Test integration and productivity requirements.Test requirements to support silicon debug and inproduction diagnostics.