The use of genetic algorithm to reduce power consumption during test application

Authors:
Jaroslav Skarvada;Zdenek Kotasek;Josef Strnadel
Affiliations:
Brno University of Technology, Faculty of Information Technology, Brno, Czech Republic;Brno University of Technology, Faculty of Information Technology, Brno, Czech Republic;Brno University of Technology, Faculty of Information Technology, Brno, Czech Republic
Venue:
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Year:
2010

Citing 6
Cited 0

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Abstract

In this paper it is demonstrated how two issues from the area of testing electronic components can be merged and solved by means of a genetic algorithm. The two issues are the ordering of test vectors and scan registers with the goal of reducing switching activity during test application and power consumption as a consequence of the ordering. The principles of developing an optimizing procedure with the aim of achieving a solution satisfying the required value of power consumption during power consumption are described here. A basic description of the methodology together with the functions needed to implement the procedures is provided. Experimental results are also discussed.