Hierarchy-aware and area-efficient test infrastructure design for core-based system chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A concurrent testing method for NoC switches
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Multiple-constraint driven system-on-chip test time optimization
Journal of Electronic Testing: Theory and Applications
The efficient TAM design for core-based SOCs testing
WSEAS Transactions on Circuits and Systems
An efficient scheduling algorithm based on multi-frequency tam for SOC testing
WSEAS Transactions on Circuits and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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Localized delay defects, like resistive shorts, resistiveopens, etc., can be effectively detected by testing the longesttestable path through each wire (or gate) in the circuit. Sucha delay test set is referred to as a longest-path-per-wire testset. ...