A General Purpose 1149.4 IC with HF Analog Test Capabilities
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test infrastructure design for mixed-signal SOCs with wrapped analog cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Block-level Bayesian diagnosis of analogue electronic circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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Abstract: This paper describes an on-chip analog bus whose bandwidth is limited primarily by an off-chip amplifier. It uses only a digital 3-state inverter for each bus input. The high-speed and constant low-input capacitance of this scheme make it suitable for measuring sensitive or even digital signals. For equal silicon area, the signal bandwidth is demonstrated to be 10 to 40 times that of previously reported transmission gate schemes.